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Preliminary
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
FEATURES
* * * * * * * * * 100MHz to 200MHz Fundamental Mode Crystal. Output range: 100MHz - 200MHz (no PLL). Low Injection Power for crystal 50uW. Complementary outputs: CMOS, PECL or LVDS. Selectable OE Logic (enable high or enable low). Integrated variable capacitors. Supports 2.5V or 3.3V-Power Supply. Available in die form. Die thickness is 10 mil.
62 mil
DIE CONFIGURATION
65 mil
DNC
DNC
VDD
VDD
VDD
VDD
N/C
N/C
(1550,1475)
17 16
25
24
23
22
21
20
19
18
GNDBUF N/C LVDSB PECLB VDDBUF VDDBUF PECL LVDS OUTSEL^
XIN XOUT DNC DNC OE CTRL VCON
26
27
Die ID: A1919-19B
15
28
14
13 29 12
DESCRIPTIONS
PLL520-20 is a VCXO IC specifically designed to pull high frequency fundamental crystals. Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input.
11 30
C502A
31 1 2 3 4 5 6 7 8
10 9
Reserved
Y
(0,0)
X
DIE SPECIFICATIONS
Name Value 62 x 65 mil GND 80 micron x 80 micron 10 mil Size Reverse side Pad dimensions Thickness
BLOCK DIAGRAM
OE VCON Oscillator X+ XQ Q
Amplifier w/ integrated varicaps
PLL520-20
OUTPUT SELECTION AND ENABLE
Pad #18 OUTSEL1 0 0 1 1 OE_SELECT (Pad #9) 0 1 (Default) Pad #25 OUTSEL0 0 1 0 1 OE_CTRL (Pad #30) 0 1 (Default) 0 (Default) 1 Selected Output High Drive CMOS Standard CMOS LVDS PECL (default) State Tri-state Output enabled Output enabled Tri-state
Pad #9, 18, 25: Bond to GND to set to "0", bond to VDD to set to "1" No connection results to "default" setting through internal pull-up/-down. Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is "1" Logical states defined by CMOS levels if OE_SELECT is "0"
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 1
GNDBUF
GNDBUF
GND
GND
GND
GND
GND
Preliminary
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection
SYMBOL
VDD VI VO TS TA TJ
MIN.
VSS-0.5 VSS-0.5 -65 0
MAX.
4.6 VDD+0.5 VDD+0.5 150 70 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
2. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Crystal Pullability Recommended ESR
SYMBOL
FXIN CL (xtal) C0 C0/C1 (xtal) RE AT cut AT cut
CONDITIONS
Parallel Fundamental Mode Die at VCON = 1.65V
MIN.
120
TYP.
MAX.
200
UNITS
MHz pF
4 3.5 250 30
pF
3. Voltage Control Crystal Oscillator PARAMETERS
VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW 0V VCON 3.3V, -3dB 25
SYMBOL
TVCXOSTB
CONDITIONS
From power valid XTAL C0/C1 < 250 0V VCON 3.3V at room temperature VCON = 0 to 3.3V
MIN.
180*
TYP.
10
MAX.
UNITS
ms ppm
100* 4 - 18* 4* 65 60 5*
ppm pF % ppm/V k kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 2
Preliminary
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
4. General Electrical Specifications PARAMETERS
Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current
SYMBOL
IDD VDD
CONDITIONS
PECL/LVDS
MIN.
3.13
TYP.
MAX.
100/80/40 3.47
UNITS
mA V % mA
@ 1.25V (LVDS) @ Vdd - 1.3V (PECL)
45 45
50 50 50
55 55
5. Jitter specifications PARAMETERS
Period jitter RMS at 155MHz Period jitter peak-to-peak at 155MHz Accumulated jitter RMS at 155MHz Accumulated jitter peak-to-peak at 155MHz Random Jitter Integrated jitter RMS at 155MHz
Measured on Wavecrest SIA 3000
CONDITIONS
At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. "RJ" measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5 18.5 2.5 24 2.5 0.3
MAX.
20
UNITS
ps
27
ps ps
0.4
ps
6. Phase noise specifications PARAMETERS Phase Noise relative to carrier FREQUENCY 155.52MHz @10Hz -75 @100Hz -95 @1kHz -125 @10kHz -140 @100kHz -145 UNITS dBc/Hz
Note: Phase Noise measured at VCON = 0V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 3
Preliminary
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
7. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage V DD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current 8. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL V OD V OD V OH V OL V OS V OS I OXD I OSD
CONDITIONS
MIN. 247 -50
TYP. 355 1.4
MAX. 454 50 1.6 1.375 25 10 -8
UNITS mV mV V V V mV uA mA
R L = 100 (see figure)
0.9 1.125 0
1.1 1.2 3 1 -5.7
V out = V DD or GND V DD = 0V
SYMBOL
tr tf
CONDITIONS R L = 100 C L = 10 pF (see figure)
MIN. 0.2 0.2
TYP. 0.7 0.7
MAX. 1.0 1.0
UNITS ns ns
LVDS Switching Test Circuit
OUT
50
CL = 10pF
VOD
VOS
VDIFF
RL = 100
50 CL = 10pF OUT OUT
LVDS Transistion Time Waveform
OUT 0V (Differential) OUT
80% VDIFF 20% 0V
80%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 4
Preliminary
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
9. PECL Electrical Characteristics PARAMETERS Output High Voltage Output Low Voltage SYMBOL V OH V OL CONDITIONS R L = 50 to (V DD - 2V) (see figure) MIN. V DD - 1.025 V DD - 1.620 MAX. UNITS V V
10. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time SYMBOL
tr tf
CONDITIONS @20/80% - PECL @80/20% - PECL
MIN.
TYP. 0.6 0.5
MAX. 1.5 1.5
UNITS ns ns
PECL Levels Test Circuit
OUT VDD OUT
PECL Output Skew
50
2.0V 50%
50 OUT OUT tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT 80% 50% 20% OUT tR tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 5
Preliminary
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
PAD ASSIGNMENT
Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name GND GND GND GND GND N/C GND GNDBUF OE_SELECT LVDS PECL VDDBUF VDDBUF PECLB LVDSB CMOS GNDBUF OUTSEL1 DNC (Do Not Connect) DNC (Do Not Connect) VDD VDD VDD VDD OUTSEL0 XIN XOUT DNC (Do Not Connect) DNC (Do Not Connect) OE_CTRL VCON X (m) 248 361 473 587 702 874 1042 1171 1400 1400 1400 1400 1400 1400 1400 1400 1389 1232 1042 854 659 559 459 358 194 109 109 109 109 109 109 Y (m) 109 109 109 109 109 109 109 109 125 259 476 616 716 871 1089 1227 1365 1365 1365 1365 1365 1365 1365 1365 1365 1223 1017 858 646 397 181
Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 6
Preliminary
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
ORDERING INFORMATION
PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PLL520-20
PART NUMBER
DC
TEMPERATURE
C=COMMERCIAL
PACKAGE TYPE
D=DIE
Order Number PLL520-20DC
Marking PLL520-20DC
Package Option Die - Waffle Pack
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 7

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